1. Field of the Invention
The present invention relates to the process of transferring data between integrated circuits. More specifically, the present invention relates to a method and an apparatus for aligning capacitive transmitter mini-bars on a first chip with capacitive receiver mini-bars on a second chip to facilitate compensation for variations in alignment between the first chip and the second chip.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems into a single chip. Such integration can potentially increase the operating speed of the system, because signals between system components do not have to travel across chip boundaries, and therefore are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems into a single chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in integration technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically soldered onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This communication bottleneck is expected to worsen as chip integration densities continue to increase.
To overcome this bottleneck, researchers have begun to investigate alternative techniques for inter-chip communications. One promising technique is to transmit signals through arrays of capacitively coupled transmitter and receiver pads. If a first chip is mounted face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines through a printed circuit board.
However, it is not a simple matter to align the chips properly. One alignment technique is to reduce the size of transmitter pads and to arrange them in a dense array. These smaller transmitter pads communicate with larger receiver pads. When two chips are aligned, only those transmitter pads that can capacitively couple with proximate receiver pads are driven with signals to transmit. In this way, misalignment of the receiver pad can be compensated for by selectively activating transmitter pads which substantially overlap with a receiver pad (see FIG. 2).
Unfortunately, this approach has limitations, especially as the number of bit positions increases. (A bit position is one capacitively coupled communication channel, which is capable of communicating a single bit-serial signal.) A switching circuit is typically used to selectively transmit different signals through transmitter pads to a targeted receiver pad. As the number of bit positions increases, there are two ways to accommodate more receiver pads. One way is to increase the coverage resolution of the transmitter pads, so that more receiver pads can be packed into a given area without too much interference. This translates to more, smaller transmitter pads, and a denser transmitter-pad array. The other way is to take up more chip-surface area to accommodate more receiver pads. Either approach causes the number of transmitter pads, and therefore the corresponding complexity of the switching circuitry, to increase non-linearly. Therefore, this is not a very scalable solution.
Hence, what is needed is a scalable approach for effectively aligning two chips for communications through capacitive coupling without introducing complex switching circuitry within the transmitting chip.